In recent years, the reduced sizes and increased performances of electronic devices have generated a demand for higher integration, higher density, and higher processing speed in the semiconductor devices used for such electronic devices. To meet such a demand, packages for semiconductor devices are being developed from a pin insertion type to a surface packaging type for purposes of increasing the packaging densities thereof, and also developments have been proposed for a DIP (Dual Inline Package) type to a QFP (Quad Flat Package) type and a PGA (Pin Grid Array) type package for coping with the requirements of a multi-pin arrangement.
Of the packages thus developed, the QFP type makes it difficult to cope with a multi-pin arrangement because it is so configured that leads to be connected to a packaging substrate are concentrated only at a peripheral portion of the package when they are also liable to be deformed due to the small diameter thereof. On the other hand, the PGA type has a limitation in that it presents difficulties in coping with both high speed processing and surface packaging because it is so configured that the terminals to be connected to a packaging substrate are elongated and very collectively arranged.
Recently, to solve these problems and to realize a semiconductor device capable of coping with high speed processing, a ball grid array (BGA) package has been disclosed in U.S. Pat. No. 5,148,265, which has ball-like connection terminals over the entire packaging surface of a carrier substrate electrically connected to a semiconductor chip by gold wire bonding. In a BGA package the terminals to be connected to the packaging substrate are formed into ball-like shapes and are arrayed over substantially the entire packaging surface without deforming the leads as the case for the QFP. Therefore the pitch between the terminals become larger, thereby making surface packaging easier. Furthermore, because the connection terminals are shorter than in a QFP package, the inductance component becomes smaller and thereby the signal transmission speed becomes greater. The resulting BGA package is therefore amenable to high speed processing.
A conventional BGA package base includes a substrate made of an electrically insulating material such as alumina ceramic and a number of connection terminals or bumps formed on the main surface of the substrate. Each connection terminal includes a solder ball bonded to a bonding pad by way of a mass of solder. The bonding pad is formed on a main surface of a substrate treated by a predetermined plating process. The mass of solder typically consists of Pb—Sn eutectic solder or a similar, low melting point solder. The solder ball, itself, is made of a relatively high melting point solder, typically containing a high percentage of lead (Pb), as for example Pb90-Sn10. The solder ball is bonded to the plated surface of the bonding pad by means of the solder mass, thereby constituting a connection terminal. In use, the wired board is mounted on a printed board having bonding pads corresponding in arrangement to those of the wired board in such a manner that their connection terminals are respectively aligned with each other, and then the respective terminals are bonded, electrically connecting the wire board to the printed board.
In the prior art BGA packages, an elastic body is inserted between a semiconductor chip and terminals of a packaging substrate for relieving thermal stress produced due to a difference in thermal expansion between the laminate package substrate and the semiconductor chip. Semiconductor devices having such structures still have problems because of the thermal mismatch. There is much in the literature about the effect of thermal stressing on BGA life. The thermal stresses, attendant to multiple power on/off cycles, literally tear the pads off the package causing loss of electrical connection and failure. The industry is trying to overcome this by increasing the pad adhesion to the substrate surface. In contradistinction to current industry practice, the present invention solves the problem of thermal stress-induced failure by decreasing the adhesion to the laminate.
FIG. 1 illustrates a conventional fabrication technique. Substrate 100 is shown with a copper foil having a smooth surface 103 and a rough, dendritic surface 105 bonded to a dielectric 107. It is understood that dielectric 107 can be the dielectric of a single or multilayer substrate. The surface of dielectric 107 is imparted with a rough texture through lamination with the dendritic side of the external copper foil. Turning to FIG. 2 conventional subtractive circuitization is illustrated. A negative acting photoresist 209 is applied to the upper surface of copper foil 203. After development, openings 211 are formed in the resist. FIG. 3 illustrates the prior art BGA pad after etching and stripping of the resist. BGA pad 309 is shown anchored to dielectric 307 by the dendritic copper surface 305. It is understood that substantially the entire surface topography of dielectric substrate 300 is dominated by a “replica” of the dendritic surface. The dendritic topography provides enhanced adhesion. During thermal stressing of the laminate, such as power on/off cycling, the BGA pads remain ‘anchored’ to the laminate surface through this dendritic structure. As the laminate surface expands and contracts with the thermal excursions the BGA pad moves with the surface. This can place excessive stress on the package. The solder ball anchors the pad to the chip. As the BGA pad moves with the laminate, the stress can fracture the solder connection causing failure. Accordingly, it would be desirable to provide enhanced BGA life. The present invention achieves this goal by reducing the adhesion of the BGA pad to the laminate.